1. Field of the Invention
The present invention relates to a semiconductor device that is easy to fabricate and consumes low power.
2. Description of the Related Art
Semiconductor devices these days employ fine elements to realize high integration and operation speed. However, it is required to further scale down the elements of the semiconductor devices.
Scaling down the elements, however, has some limits due to the dielectric strength of each element and a terminal-to-terminal dielectric strength. In each element, the strength of an electric field applied to an insulation film must be below a predetermined value, and accordingly, a power source voltage for the element must be below a predetermined value. The limited power source voltage means a slow operation speed.
To realize a low-voltage high-speed operation, conventional semiconductor devices employ ED-(enhancement-depletion) MOS circuits, EE-MOS circuits, and CMOS circuits.
The EE-MOS circuit employs an enhancement FET as a load resistor. This FET is of the same kind as a FET serving as a switching element. The ED-MOS circuit employs a depletion FET as a load resistor. The EE- and ED-MOS circuits may each employ two MISFETs having channels of the same conduction type to simplify fabrication processes. The load FET is ON even during a non-operation period, to cause a problem of large power consumption. Portable word processors and notebook computers employ primary batteries or secondary batteries such as nickel-cadmium batteries. To extend the life of these batteries, semiconductor devices for these portable machines must be of low power consumption.
The CMOS circuit employs two FETs of different conduction types, i.e., an n-channel FET and a p-channel FET connected in series. The gates of the FETs are connected to a signal input terminal, and the two FETs operate complementarily. More precisely, only one of the FETs is ON to cause no through current and reduce power consumption. The CMOS circuit, however, involves complicated fabrication processes because it employs a mixture of n- and p-channel FETs. In addition, fine adjustment is needed to properly control the characteristics of the p- and n-channel FETs. The p-channel FET is poor in driving ability compared with the n-channel FET, so that the p-channel FET must have a wide element width to pass a large current. This results in increasing the area of the element.
In this way, there are no conventional semiconductor devices that meet the requirements of simplifying fabrication processes and reducing power consumption.